Sample Term Paper
There is another very advanced multithreading model called superscalar multithreading, where a processor issue multiple instructions from a single thread in each CPU cycle. There is also a slight variation called simultaneous multithreading where in each CPU cycle the superscalar multiprocessor issue instruction from different threads. Since a single thread has limited amount of instruction level parallelism this model utilizes parallelism available across multiple threads and minimizes the possible waste associated with each slot allocated for processing.
Simultaneous multithreading is a processor design that combines hardware multithreading with superscalar processor technology to allow multiple threads to issue instructions each cycle. Unlike other hardware multithreaded architectures (such as the Tera MTA), in which only a single hardware context (i.e., thread) is active on any given cycle, SMT permits all thread contexts to simultaneously compete for and share processor resources. Unlike conventional superscalar processors, which suffer from a lack of per-thread instruction-level parallelism, simultaneous multithreading uses multiple threads to compensate for low single-thread ILP (Susan Eggers, 2005).
When instructions from any one of the threads is issued, its called temporal multithreading. System implementing this type of multithreading include Alpha AXP EV8 (uncompleted), Intel Hyperthreading, IBM POWER5, Power Processing Element within the Cell microprocessor and Sun Microsystems
HyperThreading Technology (HTT) is Intel’s trademark for their implementation of the simultaneous multithreading technology (SMT) on the Pentium 4 micro architecture. It is basically a more advanced form of SuperThreading that first debuted on the Intel Xeon processors and was later added to Pentium 4 processors (OSDEV, 2006).
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